Semiconductor device and method for fabricating the same

ABSTRACT

A semiconductor device and a method for fabricating the same are provided. The semiconductor device includes first and second gate stack structures formed in first and second regions, respectively, wherein the first gate stack structure is formed adjacent a first channel region and comprises a first gate insulating film having a first thickness formed on the first channel region, a first function film having a second thickness formed on the first gate insulating film and a first filling film having a third thickness formed on the first function film, wherein the second gate stack structure is formed adjacent a second channel region and comprises a second gate insulating film having the first thickness formed on the second channel region, a second function film having the second thickness formed on the second gate insulating film and a second filling film having the third thickness formed on the second function film, wherein the first and second function films, respectively, comprise TiN and Si concentrations that are different from each other.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority from Korean Patent Application No.10-2016-0147309 filed on Nov. 7, 2016 in the Korean IntellectualProperty Office, and all the benefits accruing therefrom under 35 U.S.C.119, the contents of which in its entirety are herein incorporated byreference.

BACKGROUND 1. Technical Field

The present disclosure relates to a semiconductor device and a methodfor fabricating the same.

2. Description of the Related Art

As one of the scaling technologies to increase the density ofsemiconductor devices, the multi-gate transistor has been suggested inwhich silicon bodies in a fin or nanowire shape are formed on asubstrate, with gates then being formed on surfaces of the siliconbodies.

Such multi-gate transistor allows easy scaling, as it uses athree-dimensional channel. Further, current control capability can beenhanced without requiring increased gate length of the multi-gatetransistor. Furthermore, it is possible to effectively suppress shortchannel effect (SCE) which is the phenomenon that the electric potentialof the channel region is influenced by the drain voltage.

SUMMARY

It is one technical object of the present disclosure to provide asemiconductor device with improved operating characteristics.

It is another technical object of the present disclosure to provide amethod for fabricating a semiconductor device with improved operatingcharacteristics.

The objects according to the present disclosure are not limited to thoseset forth above and objects other than those set forth above will beclearly understood to a person skilled in the art from the followingdescription.

According to an exemplary embodiment, there is provided a semiconductordevice comprising first and second gate stack structures formed in firstand second regions, respectively, wherein the first gate stack structurecomprises a first channel region, a first gate insulating film having afirst thickness formed on the first channel region, a first functionfilm having a second thickness formed on the first gate insulating filmand a first filling film having a third thickness formed on the firstfunction film, wherein the second gate stack structure comprises asecond channel region, a second gate insulating film having the firstthickness formed on the second channel region, a second function filmhaving the second thickness formed on the second gate insulating filmand a second filling film having the third thickness formed on thesecond function film, wherein the first and second function filmscomprise TiN, and Si concentrations of the first and second functionfilms are different from each other.

According to another exemplary embodiment, there is provided asemiconductor device, comprising a substrate comprising first and secondregions, first and second channel regions formed in the first and secondregions, respectively, first and second gate insulating films formed onthe first and the second channel regions, respectively, first and secondfunction films formed on the first and second gate insulating films,respectively and comprising TiN, wherein a Si concentration of the firstfunction film and a Si concentration of the second function film aredifferent from each other and first and second filling films formed onthe first and the second function films, respectively, wherein the firstand second function films are TiSiN single film, or multiple filmsincluding a TiN film and a Si film alternately stacked.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, features and advantages of the presentdisclosure will become more apparent to those of ordinary skill in theart by describing in detail exemplary embodiments thereof with referenceto the accompanying drawings, in which:

FIG. 1 is a concept view of a stack structure provided to explain asemiconductor device according to some exemplary embodiments;

FIG. 2 is a concept view of a stack structure provided to explain asemiconductor device according to some exemplary embodiments;

FIG. 3 is a graph provided to explain threshold voltage change accordingto a thickness ratio of the stack structure of FIG. 2;

FIG. 4 is a concept view of a stack structure provided to explain asemiconductor device according to some exemplary embodiments;

FIG. 5 is a perspective view illustrating a semiconductor deviceaccording to some exemplary embodiments;

FIG. 6 is a cross sectional view taken on lines A1-A1 and A2-A2 of FIG.5;

FIG. 7 is a cross sectional view taken on lines B1-B1 and B2-B2 of FIG.5;

FIG. 8 is a cross sectional view taken on lines C1-C1 and C2-C2 of FIG.5;

FIG. 9 is a cross sectional view provided to explain a semiconductordevice according to some exemplary embodiments;

FIG. 10 is a layout diagram provided to explain a semiconductor deviceaccording to some exemplary embodiments;

FIG. 11 is a cross sectional view taken on lines D1-D1 and D2-D2 of FIG.10;

FIG. 12 is a cross sectional view provided to explain a semiconductordevice according to some exemplary embodiments;

FIG. 13 is a layout diagram provided to explain a semiconductor deviceaccording to some exemplary embodiments;

FIG. 14 is a cross sectional view taken on lines E1-E1 and E2-E2 of FIG.13;

FIG. 15 is a cross sectional view provided to explain a semiconductordevice according to some exemplary embodiments;

FIGS. 16 to 18 are views illustrating intermediate stages offabrication, provided to explain a method for fabricating asemiconductor device according to some exemplary embodiments; and

FIGS. 19 to 22 are views illustrating intermediate stages offabrication, provided to explain a method for fabricating asemiconductor device according to some exemplary embodiments.

DETAILED DESCRIPTION

The present disclosure now will be described more fully hereinafter withreference to the accompanying drawings, in which various exemplaryembodiments are shown. The invention may, however, be embodied in manydifferent forms and should not be construed as limited to the exemplaryembodiments set forth herein. These example exemplary embodiments arejust that—examples—and many embodiments and variations are possible thatdo not require the details provided herein. It should also be emphasizedthat the disclosure provides details of alternative examples, but suchlisting of alternatives is not exhaustive. Furthermore, any consistencyof detail between various exemplary embodiments should not beinterpreted as requiring such detail—it is impracticable to list everypossible variation for every feature described herein. The language ofthe claims should be referenced in determining the requirements of theinvention.

In the drawings, the size and relative sizes of layers and regions maybe exaggerated for clarity. Like numbers refer to like elementsthroughout. Though the different figures show variations of exemplaryembodiments, these figures are not necessarily intended to be mutuallyexclusive from each other. Rather, as will be seen from the context ofthe detailed description below, certain features depicted and describedin different figures can be combined with other features from otherfigures to result in various embodiments, when taking the figures andtheir description as a whole into consideration.

Although the figures described herein may be referred to using languagesuch as “one embodiment,” or “certain embodiments,” these figures, andtheir corresponding descriptions are not intended to be mutuallyexclusive from other figures or descriptions, unless the context soindicates. Therefore, certain aspects from certain figures may be thesame as certain features in other figures, and/or certain figures may bedifferent representations or different portions of a particularexemplary embodiment.

The terminology used herein is for the purpose of describing particularexemplary implementations only and is not intended to be limiting of theinvention. As used herein, the singular forms “a”, “an” and “the” areintended to include the plural forms as well, unless the context clearlyindicates otherwise. As used herein, the term “and/or” includes any andall combinations of one or more of the associated listed items and maybe abbreviated as “/”.

It will be understood that, although the terms first, second, third etc.may be used herein to describe various elements, components, regions,layers and/or sections, these elements, components, regions, layersand/or sections should not be limited by these terms. Unless the contextindicates otherwise, these terms are only used to distinguish oneelement, component, region, layer or section from another element,component, region, layer or section, for example as a naming convention.Thus, a first element, component, region, layer or section discussedbelow in one section of the specification could be termed a secondelement, component, region, layer or section in another section of thespecification or in the claims without departing from the teachings ofthe present invention. In addition, in certain cases, even if a term isnot described using “first,” “second,” etc., in the specification, itmay still be referred to as “first” or “second” in a claim in order todistinguish different claimed elements from each other.

It will be further understood that the terms “comprises” and/or“comprising,” or “includes” and/or “including” when used in thisspecification, specify the presence of stated features, regions,integers, steps, operations, elements, and/or components, but do notpreclude the presence or addition of one or more other features,regions, integers, steps, operations, elements, components, and/orgroups thereof.

It will be understood that when an element is referred to as being“connected” or “coupled” to or “on” another element, it can be directlyconnected or coupled to or on the other element or intervening elementsmay be present. In contrast, when an element is referred to as being“directly connected” or “directly coupled” to another element, or as“contacting” or “in contact with” another element, there are nointervening elements present. Other words used to describe therelationship between elements should be interpreted in a like fashion(e.g., “between” versus “directly between,” “adjacent” versus “directlyadjacent,” etc.).

Embodiments described herein will be described referring to plan viewsand/or cross-sectional views by way of ideal schematic views.Accordingly, the exemplary views may be modified depending onmanufacturing technologies and/or tolerances. Therefore, the disclosedexemplary implementations are not limited to those shown in the views,but include modifications in configuration formed on the basis ofmanufacturing processes. Therefore, regions exemplified in figures mayhave schematic properties, and shapes of regions shown in figures mayexemplify specific shapes of regions of elements to which aspects of theinvention are not limited.

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,”“upper” and the like, may be used herein for ease of description todescribe one element's or feature's relationship to another element(s)or feature(s) as illustrated in the figures. It will be understood thatthe spatially relative terms are intended to encompass differentorientations of the device in use or operation in addition to theorientation depicted in the figures. For example, if the device in thefigures is turned over, elements described as “below” or “beneath” otherelements or features would then be oriented “above” the other elementsor features. Thus, the term “below” can encompass both an orientation ofabove and below. The device may be otherwise oriented (rotated 90degrees or at other orientations) and the spatially relative descriptorsused herein interpreted accordingly.

Also these spatially relative terms such as “above” and “below” as usedherein have their ordinary broad meanings—for example element A can beabove element B even if when looking down on the two elements there isno overlap between them (just as something in the sky is generally abovesomething on the ground, even if it is not directly above).

Although corresponding plan views and/or perspective views of somecross-sectional view(s) may not be shown, the cross-sectional view(s) ofdevice structures illustrated herein provide support for a plurality ofdevice structures that extend along two different directions as would beillustrated in a plan view, and/or in three different directions aswould be illustrated in a perspective view. The two different directionsmay or may not be orthogonal to each other. The three differentdirections may include a third direction that may be orthogonal to thetwo different directions. The plurality of device structures may beintegrated in a same electronic device. For example, when a devicestructure (e.g., a memory cell structure or a transistor structure) isillustrated in a cross-sectional view, an electronic device may includea plurality of the device structures (e.g., memory cell structures ortransistor structures), as would be illustrated by a plan view of theelectronic device. The plurality of device structures may be arranged inan array and/or in a two-dimensional pattern.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which this disclosure belongs. It willbe further understood that terms, such as those defined in commonly useddictionaries, should be interpreted as having a meaning that isconsistent with their meaning in the context of the relevant art and/orthe present application, and will not be interpreted in an idealized oroverly formal sense unless expressly so defined herein.

Hereinafter, a semiconductor device according to some exemplaryembodiments will be described with reference to FIGS. 1 to 4.

FIG. 1 is a concept view of a stack structure provided to explain asemiconductor device according to some exemplary embodiments.

The semiconductor device according to some exemplary embodimentsincludes a first region I and a second region II. The first region I andthe second region II may be the regions adjacent to each other, or theregions spaced apart from each other in the semiconductor device. Thefirst region I and the second region II may be formed in the samedirection, or different directions.

A first gate stack structure 1100 may be formed in the first region I.The first gate stack structure 1100 may be a stack structure serving asa gate electrode for the transistor. Subsequent other embodiments willbe described in detail below with reference to an actual shape of thefirst gate stack structure 1100, after the order of stacking andcharacteristics of the structure are described.

The first gate stack structure 1100 may include a first channel region1110, a first gate insulating film 1120, a first function film 1130, anda first filling film 1140.

The first channel region 1110 may be utilized as a channel region forthe transistor. For example, the first channel region 1110 may includeat least one of silicon, silicon germanium, indium antimonide, leadtelluride compound, indium arsenide, indium phosphide, gallium arsenide,or gallium antimonide. However, it is assumed herein only forconvenience of explanation that the first channel region 1110 includessilicon.

The first gate insulating film 1120 may be formed on the first channelregion 1110. The first gate insulating film 1120 may directly contactthe first channel region 1110. The first gate insulating film 1120 mayprevent the first channel region 1110 from directly contacting the firstfunction film 1130. Thus, the first gate insulating film 1120 may serveto insulate the gate of the transistor from the channel region betweenthe source region and the drain region.

It is of course possible the first gate insulating film 1120 may includean insulator. For example, the first gate insulating film 1120 mayinclude silicon oxide, silicon nitride, or silicon oxynitride, or ahigh-k material.

In an example, the high-k material may be material that has a higherdielectric constant (k) than the silicon oxide. For example, the high-kmaterial may include one or more of hafnium oxide, hafnium siliconoxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide,zirconium silicon oxide, tantalum oxide, titanium oxide, bariumstrontium titanium oxide, barium titanium oxide, strontium titaniumoxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, andlead zinc niobate, but is not limited thereto.

The first gate insulating film 1120 may be formed with a first thicknessH1. The first thickness H1 may be a thickness of the second gateinsulating film 1220 that will be described below.

The first function film 1130 may be formed on the first gate insulatingfilm 1120. The first function film 1130 may be in contact with the firstgate insulating film 1120. The first function film 1130 may be spacedapart from the first channel region 1110 by the first gate insulatingfilm 1120.

The first function film 1130 may be formed with a second thickness H2.The second thickness H2 may be a thickness of the second function film1230 that will be described below.

The first function film 1130 may include TiSiN. At this time, the Siconcentration of the first function film 1130 may be deemed a firstconcentration. The first concentration may be different from Siconcentration of the second function film 1230 that will be describedbelow. The first concentration of Si may be 0% so that the firstfunction film 1130 may include TiN.

In some exemplary embodiments, Ti and Si of the TiSiN may be replaced byat least two of Ta, La, Hf, Mo and Yb. Likewise, in some exemplaryembodiments, N of the TiSiN may be replaced by at least one of O, C, Sand Se. In some exemplary embodiments, TiSiN may all be replaced by thecorresponding materials. However, for convenience of explanation, thefollowing embodiment is described based on TiSiN.

The first function film 1130 may have a function of adjusting workfunction. Thus, the first function film 1130 may adjust the thresholdvoltage of the gate. At the same time, the first function film 1130 mayalso function as a barrier film that prevents oxygen from beingexcessively introduced into the first gate insulating film 1120 during aprocess such as heat treatment. Thus, the first function film 1130 mayperform both the functions of oxygen block and work function adjustment.

The first filling film 1140 may be formed on the first function film1130. The first filling film 1140 may be contacted with the firstfunction film 1130. The first filling film 1140 may be formed on thefirst function film 1130 to thus complete the first gate stack structure1100.

The first filling film 1140 may be formed with a third thickness H3. Thethird thickness H3 may be a thickness of the second filling film 1240that will be described below. The first filling film 1140 may include ametal material having a conductivity. For example, the first fillingfilm 1140 may be formed of A1, W, and so on, or multi-films formed of acombination thereof. However, exemplary embodiments are not limitedthereto.

The second gate stack structure 1200 may include a second channel region1210, a second gate insulating film 1220, a second function film 1230,and a second filling film 1240.

The second channel region 1210 may be utilized as a channel region forthe transistor. For example, the second channel region 1210 may includeat least one of silicon, silicon germanium, indium antimonide, leadtelluride compound, indium arsenide, indium phosphide, gallium arsenide,or gallium antimonide. However, it is assumed herein only forconvenience of explanation that the second channel region 1210 includessilicon. That is, the first channel region 1110 and the second channelregion 1210 may be the same structure. Note that the concept “same” mayinclude fine differences that may occur according to characteristics ofeach region.

The second gate insulating film 1220 may be formed on the second channelregion 1210. The second gate insulating film 1220 may directly contactthe second channel region 1210. The second gate insulating film 1220 mayprevent the second channel region 1210 from directly contacting thesecond function film 1230. Thus, the second gate insulating film 1220may insulate the gate of the transistor from the channel region betweenthe source region and the drain region.

The second gate insulating film 1220 may include the same material asthe first gate insulating film 1120. That is, the second gate insulatingfilm 1220 may include silicon oxide, silicon nitride, or siliconoxynitride, or a high-k material, for example.

The second gate insulating film 1220 may be formed with a firstthickness H1. The first thickness H1 may be a thickness of the firstgate insulating film 1120.

The second function film 1230 may be formed on the second gateinsulating film 1220. The second function film 1230 may be in contactwith the second gate insulating film 1220. The second function film 1230may be spaced apart from the second channel region 1210 by the secondgate insulating film 1220.

The second function film 1230 may be formed with a second thickness H2.The second thickness H2 may be a thickness of the first function film1130.

The second function film 1230 may include TiSiN. At this time, the Siconcentration of the second function film 1230 may be a secondconcentration which is different from the first concentration of Si infirst function film 1100. Thus, the Si concentration of the firstfunction film 1130 and Si concentration of the second function film 1230may be different from each other. Specifically, the second concentrationmay be higher than the first concentration.

In some exemplary embodiments, Ti and Si of the TiSiN may be replaced byat least two of Ta, La, Hf, Mo and Yb. Likewise, in some exemplaryembodiments, N of the TiSiN may be replaced by at least one of O, C, Sand Se. In some exemplary embodiments, TiSiN may all be replaced by thecorresponding materials. However, for convenience of explanation, thefollowing description is based on TiSiN.

The second function film 1230 may adjust work function. Thus, the secondfunction film 1230 may adjust the threshold voltage of the gate. At thesame time, the second function film 1230 may function as a barrier thatprevents oxygen from being excessively introduced into the second gateinsulating film 1220 during a process such as heat treatment.

The second filling film 1240 may be formed on the second function film1230. The second filling film 1240 may be contacted with the secondfunction film 1230. The second gate stack structure 1200 may becompleted when the second filling film 1240 is formed on the secondfunction film 1230.

The second filling film 1240 may be formed with a third thickness H3.The third thickness H3 may be a thickness of the first filling film1140. The second filling film 1240 may have the same thickness as thefirst filling film 1140. However, exemplary embodiments are not limitedto the example given above.

The second filling film 1240 may include a same material as the firstfilling film 1140. The second filling film 1240 may include a metalmaterial having a conductivity. For example, the second filling film1240 may be formed of A1, W, and so on, or multiple films formed of acombination thereof. However, exemplary embodiments are not limitedthereto.

The first gate stack structure 1100 and the second gate stack structure1200 may be formed with the same height as each other. Further, in eachset of corresponding films, the first gate insulating film 1120 and thesecond gate insulating film 1220, the first function film 1130 and thesecond function film 1230, and the first filling film 1140 and thesecond filling film 1240, the thickness of each member of the set may bethe same. However, exemplary embodiments are not limited to the examplegiven above. The description of each thickness in each detailedembodiment continues below.

The first function film 1130 and the second function film 1230 may havethe same thickness as each other. Meanwhile, the first function film1130 and the second function film 1230 may have the different Siconcentrations from each other. Accordingly, threshold voltages of thefirst gate stack structure 1100 and the second gate stack structure 1200may vary. That is, two films having the same thickness may havedifferent concentrations of Si from each other without adjusting thethickness of the work function adjusting film, so that differentthreshold voltages can be implemented.

Specifically, Si concentration of the second function film 1230 may behigher than Si concentration of the first function film 1130.Accordingly, the threshold voltage of the second gate stack structure1200 may be higher than that of the first gate stack structure 1100.

In some exemplary embodiments, the first function film 1130 and thesecond function film 1230 are formed to have the same thickness, so thatthe process involving patterning, deposition, and etching repeated forseveral times can be greatly reduced to one deposition process. Suchsimple process can also implement different work functions or thresholdvoltages.

Further, because the functions of the work function adjustment film andthe barrier film may be performed simultaneously with the first functionfilm 1130 and the second function film 1230, the process of forming aseparate barrier film can also be reduced.

As a result, a semiconductor device having better operatingcharacteristics at a lower cost can be provided. In addition, as thefirst function film 1130 and the second function film 1230 having thesame thickness are formed, the process of forming the first filling film1140 and second filling film 1240 is further facilitated, and moreprecise multi-threshold voltage devices can be implemented.

In this case, the first function film 1130 and the second function film1230 may be an amorphous film. As a result, the property to preventleakage current occurred in the crystallized film can be furtherstrengthened.

Hereinbelow, a semiconductor device according to some exemplaryembodiments will be described with reference to FIGS. 2 and 3. In thefollowing description, description overlapped with the exemplaryembodiments already provided above will not be described or described asbrief as possible for the sake of brevity.

FIG. 2 is a conceptual diagram of a stack structure provided to explaina semiconductor device according to some embodiments, and FIG. 3 is agraph provided to explain a threshold voltage change according to athickness ratio of the stack structure of FIG. 2. The abscissa axis inFIG. 3 represents the equivalent oxide film thickness (EOT), and theordinate axis represents the capacitance in the gate direction.

As shown in FIG. 2, the first function film 1130 and the second functionfilm 1230 of the semiconductor device according to some exemplaryembodiments may be a multi-film structure rather than a single film.

The first function film 1130 of the first gate stack structure 1100 inthe first region I may include first interfacial function film 1130including first interfacial function films 1131 a and 1131 b and firstbarrier function film 1133 including first barrier function films 1133 aand 1133 b. The first interfacial function films 1131 a and 1131 b andthe first barrier function films 1133 a and 1133 b may be alternatelystacked with each other. At this time, each of the first interfacialfunction films 1131 a and 1131 b and the first barrier function films1133 a and 1133 b may be plural. However, the present disclosure is notlimited thereto, and the first interfacial function films 1131 a and1131 b and the first barrier function films 1133 a and 1133 b may eachbe a single film.

The first interfacial function films 1131 a and 1131 b are in directcontact with the first gate insulating film 1120, and the first barrierfunction films 1133 a and 1133 b are not in contact with the first gateinsulating film 1120. The lowermost portion of the first function film1130 may be the first interfacial function films 1131 a and 1131 b.

The first interfacial function films 1131 a and 1131 b may enhance aninterfacial characteristic with the first gate insulating film 1120. Thefirst interfacial function films 1131 a and 1131 b may include TiN, forexample. However, exemplary embodiments are not limited to the examplegiven above. The TiN may be formed by atomic layer deposition (ALD). Thefirst interfacial function films 1131 a and 1131 b may be amorphous.

The first barrier function films 1133 a and 1133 b may include Si. Thefirst barrier function films 1133 a and 1133 b may perform a barrierfunction to prevent excessive diffusion of oxygen into the first gateinsulating film 1120 thereunder in a subsequent process such as heattreatment.

The first barrier function films 1133 a and 1133 b may form Si in thesoak method. The soak method is one of the methods of directly forming asingle film, unlike the method of forming two or more films by a heattreatment.

The first interfacial function films 1131 a and 1131 b may each have,respectively, thicknesses a1 and a2. In this case, the thicknesses a1and a2 may be the same as each other, or may be different from eachother. The first barrier function films 1133 a and 1133 b may each have,respectively, thicknesses b1 and b2. In this case, the thicknesses b1and b2 may be the same as each other, or may be different from eachother.

At this time, ratio of (a1+a2):(b1+b2) may be considered as a firstratio. The first ratio may be different from the second ratio of thesecond function film 1230 that will be described below.

The second function film 1230 of the second gate stack structure 1200 inthe second region II may include second interfacial function film 1231including second interfacial function films 1231 a and 1231 b and secondbarrier function film 1233 including second barrier function films 1233a and 1233 b. The second interfacial function films 1231 a and 1231 band the second barrier function films 1233 a and 1233 b may bealternately stacked with each other. At this time, each of the secondinterfacial function films 1231 a and 1231 b and the second barrierfunction films 1233 a and 1233 b may be plural. However, the presentdisclosure is not limited thereto, and the second interfacial functionfilms 1231 a and 1231 b and the second barrier function films 1233 a and1233 b may each be a single film.

The second interfacial function films 1231 a and 1231 b are in directcontact with the second gate insulating film 1220, and the secondbarrier function films 1233 a and 1233 b are not in contact with thesecond gate insulating film 1220. The lowermost portion of the secondfunction film 1230 may be the second interfacial function films 1231 aand 1231 b.

The second interfacial function films 1231 a and 1231 b may enhanceinterfacial properties with the second gate insulating film 1220. Thesecond interfacial function films 1231 a and 1231 b may include TiN, forexample. However, exemplary embodiments are not limited to the examplegiven above. TiN may be formed by ALD. The second interfacial functionfilms 1231 a and 1231 b may be amorphous.

The second barrier function films 1233 a and 1233 b may include Si. Thesecond barrier function films 1233 a and 1233 b may perform a barrierfunction to prevent excessive diffusion of oxygen into the second gateinsulating film 1220 thereunder in a subsequent process such as heattreatment. The second barrier function films 1233 a and 1233 b may formSi in the soak method.

The second interfacial function films 1231 a and 1231 b may each have,respectively, thicknesses c1 and c2. In this case, the thicknesses c1and c2 may be the same as each other, or may be different from eachother. The second barrier function films 1233 a and 1233 b may eachhave, respectively, thicknesses d1 and d2. In this case, the thicknessesd1 and d2 may be the same as each other, or may be different from eachother.

At this time, ratio of (c1+c2):(d1+d2) may be considered to be a secondratio. The second ratio may be different from the first ratio of thefirst function film 1130. Specifically, the first ratio may be lowerthan the second ratio. For example, the thickness of the first barrierfunction films 1133 a and 1133 b with respect to that of the firstinterfacial function films 1131 a and 1131 b may be less than thethickness of the second barrier function films 1233 a and 1233 b withrespect to that of the second interfacial function films 1231 a and 1231b. The Si content in each function film may correspond to the thicknessof the barrier function film. Thus, when the barrier function film isthick, the Si content may be high, and conversely, when the barrierfunction film is thin, the Si content may be low.

Although the thicknesses of the specific layers may be different fromeach other, a second thickness H2 of the first function film 1130 andthe second function film 1230 may be the same as each other.Accordingly, it is possible to compare the Si contents in the samestate.

As shown in FIG. 3, it can be seen that flatband voltage (vfb) changesas the thickness of the barrier function film gradually increases fromt1 to t2 and then to t3. Therefore, it can be confirmed that thethreshold voltage changes in accordance with the thickness of thebarrier function film. Thus, the second gate stack structure 1200,including the second function film 1230 in the second region II whichhas a lower Si content, may have a lower threshold voltage than thefirst gate stack structure 1100.

Hereinbelow, a semiconductor device according to some exemplaryembodiments will be described with reference to FIG. 4. In the followingdescription, the previous provided description of exemplary embodimentswill not be repeated or will be described as briefly as possible for thesake of brevity.

FIG. 4 is a concept view of a stack structure provided to explain asemiconductor device according to some exemplary embodiments.

As shown in FIG. 4, a material of the first interfacial function films1131 a and 1131 b and the second interfacial function films 1231 a and1231 b of the semiconductor device according to some embodiments, and amaterial of the first barrier function films 1133 a and 1133 b and thesecond barrier function films 1233 a and 1233 b may each be the same.

The first interfacial function films 1131 a and 1131 b and the secondinterfacial function films 1231 a and 1231 b may each enhanceinterfacial properties with the first gate insulating film 1120 and thesecond gate insulating film 1220. The first interfacial function films1131 a and 1131 b and the second interfacial function films 1231 a and1231 b may include TiSiN, for example. At this time, the Siconcentration of the first interfacial function films 1131 a and 1131 band the Si concentration of the second interfacial function films 1231 aand 1231 b may be different from each other. Specifically, the Siconcentration of the second interfacial function films 1231 a and 1231 bmay be higher than that of the first interfacial function films 1131 aand 1131 b. The first interfacial function films 1131 a and 1131 b andthe second interfacial function films 1231 a and 1231 b may all beamorphous.

The first interfacial function film 1131 which includes firstinterfacial films 1131 a and 1131 b and the second interfacial functionfilm 1231 which includes second interfacial function films 1231 a and1231 b, may include TiSiN, and the first barrier function film 1135which include first barrier function films 1135 a and 1135 b and thesecond barrier function film 1235 which includes second barrier functionfilms 1235 a and 1235 b, may likewise include TiSiN. However, the firstbarrier function films 1135 a and 1135 b and the second barrier functionfilms 1235 a and 1235 b may have a different phase from the firstinterfacial function films 1131 a and 1131 b and the second interfacialfunction films 1231 a and 1231 b. For example, the first barrierfunction films 1135 a and 1135 b and the second barrier function films1235 a and 1235 b may all be crystalline. The first function film 1130and the second function film 1230 may be a structure in which theamorphous film and the crystalline film are alternately stacked.

At this time, the thickness of the first barrier function films 1135 aand 1135 b with respect to that of the first interfacial function films1131 a and 1131 b may be equal to or different from the thickness of thesecond barrier function films 1235 a and 1235 b with respect to that ofthe second interfacial function films 1231 a and 1231 b.

Hereinbelow, a semiconductor device according to some exemplaryembodiments will be described with reference to FIGS. 1, and 5 to 8. Inthe following description, the previously provided description ofexemplary embodiments will not be described again or will be describedas briefly as necessary.

FIG. 5 is a perspective view provided to explain a semiconductor deviceaccording to some exemplary embodiments, and FIG. 6 is a cross sectionalview taken on lines A1-A1 and A2-A2 of FIG. 5. FIG. 7 is a crosssectional view taken on lines B1-B1 and B2-B2 of FIG. 5, and FIG. 8 is across sectional view taken on lines C1-C1 and C2-C2 of FIG. 5.

As shown in FIGS. 5 to 8, a semiconductor device according to someexemplary embodiments may include a substrate 100 including a firstregion I and a second region II.

The substrate 100 may be, for example, a bulk silicon or asilicon-on-insulator (SOI). Alternatively, the substrate 100 may includea material different from silicon, for example, silicon germanium,indium antimonide, lead telluride compound, indium arsenide, indiumphosphide, gallium arsenide, or gallium antimonide. Alternatively, thesubstrate 100 may be a base substrate having an epitaxial layer formedthereon.

The first region I and the second region II on the substrate 100 may bethe regions adjacent to each other, or the regions spaced apart fromeach other. Thus, as long as the condition that the regions be formed onthe same substrate is satisfied, the positions of the first region I andthe second region II are not limited.

The first region I on the substrate 100 may be represented by a firstdirection X1, a second direction Y1, and a third direction Z1, which areperpendicular to each other. Meanwhile, the second region II may berepresented by a fourth direction X2, a fifth direction Y2, and a sixthdirection Z2, which are perpendicular to each other. The first to thirddirections and the fourth to sixth directions of the first region I andthe second region II may be in the same directions or differentdirections.

The first region I may include a first fin-type pattern 110, a firstnanowire 120, a third nanowire 125, a first gate insulating film 147, afirst function film 131, a first filling film 130, a first gate spacer140, a first source/drain 150, and so on.

The first fin-type pattern 110 may protrude from the substrate 100. Thefirst fin-type pattern 110 may elongate in the first direction X1. Thefirst fin-type pattern 110 may include a long side extended in the firstdirection X1, and a short side extended in the second direction Y1.

The first fin-type pattern 110 may be formed by partially etching thesubstrate 100, and may include an epitaxial layer grown from thesubstrate 100. The first fin-type pattern 110 may include an elementsemiconductor material such as silicon or germanium, for example.Further, the first fin-type pattern 110 may include a compoundsemiconductor such as, for example, IV-IV group compound semiconductoror III-V group compound semiconductor.

For example, take with respect to the IV-IV group compound semiconductorthe first fin-type pattern 110 may be a binary compound or a ternarycompound including, for example, at least two or more of carbon (C),silicon (Si), germanium (Ge), and tin (Sn), or the above-mentionedbinary or ternary compound doped with IV group element.

With respect to the III-V group compound semiconductor, the fin-typepattern 110 may be a binary compound, ternary compound or quaternarycompound which is formed as a III group element which may be at leastone of aluminum (A1), gallium (Ga), and indium (In), is combined with aV group element which may be one of phosphorus (P), arsenic (As) andantimony (Sb).

In the following description, it is assumed that the first fin-typepattern 110 of a semiconductor device according to exemplary embodimentsincludes silicon.

A field insulating film 105 may at least partially surround the sidewallof the first fin-type pattern 110. The first fin-type pattern 110 may bedefined by the field insulating film 105. The field insulating film 105may include, for example, one of oxide film, nitride film, oxynitridefilm, or a combination thereof.

As illustrated in FIG. 5, the sidewall of the first fin-type pattern 110may be surrounded by the field insulating film 105, but note that thisis only for illustrative purpose, and other embodiments are not limitedthereto.

The first nanowire 120 and the third nanowire 125 may be formed on thesubstrate 100, while being spaced apart from the first fin-type pattern110. The first nanowire 120 and third nanowire 125 may be extended inthe first direction X1. Specifically, the first nanowire 120 and thethird nanowire 125 may be formed on the first fin-type pattern 110,while being spaced apart from the first fin-type pattern 110. Further,the first nanowire 120 and third nanowire 125 may be spaced apart fromeach other.

The third nanowire 125 may be spaced apart from the substrate 100further than the first nanowire 120. That is, the height from the uppersurface of the first fin-type pattern 110 to the third nanowire 125 maybe greater than the height from the upper surface of the first fin-typepattern 110 to the first nanowire 120.

The first nanowire 120 and the third nanowire 125 may be overlapped withthe fin-type pattern 110 in the third direction Z1. The first nanowire120 and the third nanowire 125 may not be formed on the field insulatingfilm 105, and may be formed on the first fin-type pattern 110.

The first nanowire 120 and the third nanowire 125 may be used as achannel region for the transistor. The materials for the first nanowire120 and the third nanowire 125 may vary depending on whether thesemiconductor device is a PMOS or an NMOS, but other exemplaryembodiments are not limited thereto.

In the semiconductor device according to exemplary embodiments, it isassumed that the first nanowire 120 and the third nanowire 125 eachinclude silicon.

The first function film 131 and the first filling film 130 may be formedon the field insulating film 105 and the first fin-type pattern 110. Thefirst filling film 130 may extend in the second direction Y1. The firstfunction film 131 and the first filling film 130 may be so formed as tosurround the periphery of the first nanowire 120 and the third nanowire125 that are spaced apart from an upper surface of the first fin-typepattern 110. The first function film 131 and the first filling film 130may also be formed in a space defined between the first nanowire 120 andthe third nanowire 125 and the first fin-type pattern 110.

Specifically, the first function film 131 may be formed first tosurround the first nanowire 120 and the third nanowire 125, and thefirst filling film 130 may be formed thereon to surround the firstfunction film 131.

The first function film 131 may include TiSiN.

The first filling film 130 may include a conductive material. Forexample, the first filling film 130 may include at least one of TiN, WN,TaN, Ru, TiC, TaC, Ti, Ag, A1, TiAl, TiAlN, TiAlC, TaCN, TaSiN, Mn, Zr,W, and A1. Alternatively, the first filling film 130 may each be formedof non-metal element such as Si, SiGe, and so on. For example, the firstfilling film 130 described above may be formed by replacement process,but not limited thereto.

The first gate spacer 140 may be formed on both sidewalls of the firstgate electrode 130 that are extended in the second direction Y1. Thefirst gate spacer 140 may be formed on either side of the first nanowire120, while facing each other. The first gate spacer 140 may each includea through hole 140 h 1 and 140 h 2 (FIGS. 6 and 8).

The first nanowire 120 may be passed through the first gate spacer 140via the first through hole 140 h 1. The first gate spacer 140 may be indirect contact with a periphery portion of the side surface of the firstnanowire 120. The inner wall of the first through hole 140 h 1 may be incontact with a portion of the outer surface periphery of the firstnanowire 120.

The first gate spacer 140 may include the first outer spacer 141 and thefirst inner spacer 142, the second inner spacer 142-1, and the fifthinner spacer 142-2. The first outer spacer 141 may directly contact withthe first inner spacer 142, the second inner spacer 142-1, and the fifthinner spacer 142-2. The first inner spacer 142 may be disposed betweenthe upper surface of the first fin-type pattern 110 and the firstnanowire 120, and may be in surface contact with the upper surface ofthe first fin-type pattern 110. The second inner spacer 142-1 may bedisposed between the upper surface of the first nanowire 120 and thethird nanowire 125, and may be surrounded by the first outer spacer 141.The fifth inner spacer 142-2 may be disposed on the third nanowire 125,and may be surrounded by the first outer spacer 141.

On a plane including the second direction Y1 and the third direction Z1(shown in FIG. 8), the first inner spacer 142 may be surrounded by thefirst nanowire 120, the first outer spacer 141, and the fin-type pattern110. The second inner spacer 142-1 may be surrounded by the firstnanowire 120, the third nanowire 125, and the first outer spacer 141.The fifth inner spacer 142-2 may be surrounded by the third nanowire 125and the first outer spacer 141.

The gate spacer 140 may include a plurality of first through holes 140 h1 and 140 h 2. The plurality of first through holes 140 h 1 and 140 h 2of the first gate spacer 140 may be defined, respectively, by: the firstouter spacer 141, the first inner spacer 142, and the second innerspacer 142-1 the first outer spacer 141, the second inner spacer 142-1and the fifth inner spacer 142-2. Ends of the first nanowire 120 and thethird nanowire 125 may be in contact with the first outer spacer 141,the first inner spacer 142, the second inner spacer 142-1, and the fifthinner spacer 142-2.

The first inner spacer 142, the second inner spacer 142-1, and the fifthinner spacer 142-2 may include the same material as one another. Thefirst outer spacer 141, the first inner spacer 142, the second innerspacer 142-1, and the fifth inner spacer 142-2 may have differentmaterials from one another. For example, the dielectric constant of thematerial contained in the first outer spacer 141 may differ from thedielectric constant of the material contained in the first inner spacer142, the second inner spacer 142-1, and the fifth inner spacer 142-2.

In the semiconductor device according to some exemplary embodiments, thematerial included in the first outer spacer 141 may have a dielectricconstant that is greater than the dielectric constant of the materialincluded in the first inner spacer 142, the second inner spacer 142-1,and the fifth inner spacer 142-2. It is possible to reduce the fringingcapacitance between the first gate electrode 130 and the firstsource/drain 150 by having differing dielectric constants for thesematerials as described above.

For example, the first outer spacer 141 may include at least one ofsilicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2),silicon oxycarbonitride (SiOCN), or a combination thereof. The firstinner spacer 142 and the second inner spacer 142-1 may include low-kdielectric material, for example. The low-k dielectric material may bethe material that has a lower dielectric constant than the siliconoxide.

The first gate insulating layer 147 may be formed between the firstnanowire 120 and the third nanowire 125 and the first function film 131(shown in FIG. 7). Further, the first gate insulating film 147 may alsobe formed between the field insulating film 105 and the first functionfilm 131, and between the first inner spacer 142, the second innerspacer 142-1, the fifth inner spacer 142-2, and the first function film130.

For example, the first gate insulating layer 147 may include a firstinterfacial layer 146 and a first high-k insulating film 145, but notlimited thereto. Thus, the first interfacial layer 146 of the first gateinsulating film 147 may be omitted depending on a material of the firstnanowire 120 and the third nanowire 125, and so on.

Because the first interfacial layer 146 may be formed on a periphery ofthe first nanowire 120 and the third nanowire 125, the first interfaciallayer 146 may be formed between the first nanowire 120 and the thirdnanowire 125 and the first function film 131, and between the firstfin-type pattern 110 and the first function film 131.

When the first nanowire 120 and the third nanowire 125 include silicon,the first interfacial layer 146 may include silicon oxide film. Thefirst interfacial layer 146 may be formed on a periphery of the firstnanowire 120 and the third nanowire 125, but may not be formed along thesidewalls of the first inner spacer 142, the second inner spacer 142-1,the fifth inner spacer 142-2, and the first outer spacer 141.

However, the first high-k insulating film 145 may be formed between thefirst nanowire 120 and the third nanowire 125 and the first functionfilm 131, between the first inner spacer 142 and the first function film131, between the second inner spacer 142-1 and the first function film131, between the fifth inner spacer 142-2 and the first function film131, between the field insulating film 105 and the first function film131, and between the first outer spacer 141 and the first function film131.

The first high-k insulating film 145 may include a high-k materialhaving a higher dielectric constant than silicon oxide film. Forexample, the high-k material may include one or more of hafnium oxide,hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide,zirconium oxide, zirconium silicon oxide, tantalum oxide, titaniumoxide, barium strontium titanium oxide, barium titanium oxide, strontiumtitanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalumoxide, or lead zinc niobate, but is not limited thereto.

As described above, when the first interfacial layer 146 is omitted, thefirst high-k insulating film 145 may include not only the high-kmaterial, but also at least one of silicon nitride (SiN), siliconoxynitride (SiON), silicon oxide (SiO2), silicon oxycarbonitride(SiOCN), or a combination thereof.

The first gate insulating film 147 may be formed along the periphery ofthe first nanowire 120 and the third nanowire 125. The first gateinsulating film 147 may be formed along the upper surface of the fieldinsulating film 105 and the upper surface of the first fin-type pattern110. Additionally, the first gate insulating film 147 may be formedalong the sidewalls of the first inner spacer 142, the second innerspacer 142-1, the fifth inner spacer 142-2, and the first outer spacer141.

A first source/drain 150 may be formed on either side of the firstfilling film 130 and the first function film 131. The first source/drain150 may be formed on the first fin-type pattern 110. The firstsource/drain 150 may include an epitaxial layer formed on an uppersurface of the first fin-type pattern 110.

An outer circumference of the first source/drain 150 may take on avariety of shapes. For example, the outer circumference of the firstsource/drain 150 may be at least one of diamond, circle, rectangle, andoctagon shapes. FIG. 5 illustrates a diamond shape (or pentagon orhexagon shape), for example.

The first source/drain 150 may be directly connected with the firstnanowire 120 and the third nanowire 125 being used as a channel region.Thus, the first source/drain 150 may be directly connected with thefirst nanowire 120 and the third nanowire 125 that are passed throughthe plurality of first through holes 140 h 1 and 140 h 2 of the firstgate spacer 140.

However, the first source/drain 150 may not be in direct contact withthe first gate insulating film 147. The first gate spacer 140 may bepositioned between the first source/drain 150 and the first gateinsulating film 147. More specifically, because one sidewall of thefirst inner spacer 142, the second inner spacer 142-1, and the fifthinner spacer 142-2 may be in contact with the first gate insulating film147, while the other sidewall of the first inner spacer 142, the secondinner spacer 142-1, and the fifth inner spacer 142-2 may be in contactwith the first source/drain 150, the first source/drain 150 and thefirst gate insulating film 147 may not be in contact with each otherbetween the first nanowire 120 and the third nanowire 125 and thesubstrate 100.

The first interlayer insulating film 180 may be formed on the firstsource/drain 150, the first gate spacer 140, and the field insulatingfilm 105.

The first interlayer insulating film 180 may include at least one oflow-k material, oxide film, nitride film, and oxynitride film. Forexample, the low-k material may be flowable oxide (FOX), tonen silazene(TOSZ), undoped silica glass (USG), borosilica glass (BSG),phosphosilica glass (PSG), borophosphosilica glass (BPSG), plasmaenhanced tetraethyl orthosilicate (PETEOS), fluoride silicate glass(FSG), high density plasma (HDP) oxide, plasma enhanced oxide (PEOX),flowable CVD (FCVD) oxide, or a combination thereof.

The device formed in the second region II may be similar to that in thefirst region I. Specifically, the second region II may include a secondfin-type pattern 210, a second nanowire 220, a fourth nanowire 225, asecond gate insulating film 247, a second function film 231, a secondfilling film 230, a second gate spacer 240, a second source/drain 250,and all the other structures which correspond to the structures shown infirst region I.

For example, the second fin-type pattern 210, the second nanowire 220,the fourth nanowire 225, the second gate insulating film 247, the secondfunction film 231, the second filling film 230, the second gate spacer240, and the second source/drain 250 may have same or similarcharacteristics as the first fin-type pattern 110, the first nanowire120, the third nanowire 125, the first function film 131, the firstfilling film 130, the first gate spacer 140, and the first source/drain150 described above.

Further, the second interlayer insulating film 280, the second throughholes 240 h 1 and 240 h 2, the second interfacial layer 246, the secondhigh-k insulating film 245, the third inner spacer 242, the fourth innerspacer 242-1, the sixth inner spacer 242-2, and the second outer spacer241 may also have same or similar characteristics as the firstinterlayer insulating film 180, the first interfacial layer 146, thefirst high-k insulating film 145, the first inner spacer 142, the secondinner spacer 142-1, the fifth inner spacer 142-2, and the first outerspacer 141, respectively.

However, while the second function film 231 may include TiSiN like thefirst function film 131, the Si concentration may be lower. A thicknessof the second function film 231 may be equal to a thickness of the firstfunction film 131.

The semiconductor device shown in FIGS. 5 to 8 may correspond to thatshown in FIG. 1. Specifically, the first region I and the second regionII in FIGS. 5 to 8 may correspond to the first region I and the secondregion II in FIG. 1, respectively. The first nanowire 120 and the thirdnanowire 125 correspond to the first channel region 1110, and the secondnanowire 220 and the fourth nanowire 225 correspond to the secondchannel region 1210.

Further, the first gate insulating film 147 and the second gateinsulating film 247 in FIGS. 5 to 8 correspond to the first gateinsulating film 1120 and the second gate insulating film 1220 in FIG. 1.Further, the first function film 131 and the second function film 231 inFIGS. 5 to 8 correspond to the first function film 1130 and the secondfunction film 1230 in FIG. 1. Further, the first filling film 130 andthe second filling film 230 in FIGS. 5 to 8 correspond to the firstfilling film 1140 and the second filling film 1240 in FIG. 1.

The gate stack structure of FIG. 1 may be implemented as thegate-all-around structure of FIGS. 5 to 8. In the drawings, the numberof nanowires is shown as two, but this is provided only for illustrativepurpose and exemplary embodiments are not limited thereto. In someembodiments of the present disclosure, the number of nanowires may beone, or more than two.

Hereinbelow, a semiconductor device according to some exemplaryembodiments will be described with reference to FIGS. 2 and 9. In thefollowing description, the description of previously disclosed exemplaryembodiments that has already been provided above will not be describedhere or will be described as briefly as needed for the sake of brevity.

FIG. 9 is a cross sectional view provided to explain a semiconductordevice according to some exemplary embodiments.

As shown in FIGS. 2 and 9, the first function film 1130 and the secondfunction film 1230 of FIG. 2 may be formed in a gate-all-aroundstructure, which is the semiconductor device shown in FIG. 9.

The first function film 131 may have a structure in which the firstinterfacial function film 131 a and the first barrier function film 131b are alternately stacked. Although each of the first interfacialfunction film 131 a and the first barrier function film 131 b is shownas a pair in the drawings, in some embodiments, each of the firstinterfacial function film 131 a and the first barrier function film 131b may be more than two, or may be one.

The second function film 231 may have a structure in which the secondinterfacial function film 231 a and the second barrier function film 231b are alternately stacked. Although each of the second interfacialfunction film 231 a and the second barrier function film 231 b is shownas a pair in the drawings, in some embodiments, each of the secondinterfacial function film 231 a and the second barrier function film 231b may be more than two, or may be one.

Hereinbelow, a semiconductor device according to some exemplaryembodiments will be described with reference to FIGS. 1, 10 and 11. Inthe following description, the previous description of exemplaryembodiments already provided above will not be described here or will bedescribed as briefly as needed for the sake of brevity.

FIG. 10 is a layout view provided to explain a semiconductor deviceaccording to some exemplary embodiments, and FIG. 11 is a crosssectional view taken on lines D1-D1 and D2-D2 of FIG. 10.

As shown in FIGS. 1, 10 and 11, a semiconductor device according to someexemplary embodiments includes a substrate 10, an interlayer insulatingfilm 20, spacers 21 and 22, high-k films 31 and 32, gate patterns 61 and62, capping patterns 81 and 82, and source/drains 91 and 92.

The substrate 10 includes a first region I and a second region II,wherein the first region I includes a first fin F1 protruding from thesubstrate 10 and the second region II includes a second fin F2protruding from the substrate 10. The first gate pattern 61 may extendon the first fin F1 in a direction intersecting the first fin F1, andthe second gate pattern 62 may extend on the second fin F2 in adirection intersecting the second fin F2.

The interlayer insulating film 20 may be formed on the substrate 10. Theinterlayer insulating film 20 may include a first trench T1 in the firstregion I, and a second trench T2 in the second region II. The interlayerinsulating film 20 may be formed by stacking two or more insulatingfilms. As illustrated, the first spacer 21 and the second spacer 22 maybe formed on sidewalls of the first trench T1 and the second trench T2,respectively, and the substrate 10 may be disposed on bottom surfaces ofthe first trench T1 and the second trench T2. However, exemplaryembodiments are not limited to the example given above.

The interlayer insulating film 20 may include at least one of siliconoxide, silicon nitride, silicon oxynitride, and a low-k dielectricmaterial with a smaller dielectric constant than silicon oxide.

The first spacer 21 may form a sidewall of the first trench T1 and mayinclude at least one of silicon nitride (SiN), silicon oxynitride(SiON), silicon oxide (SiO2), silicon oxycarbonitride (SiOCN), or acombination thereof.

The second spacer 22 may form a sidewall of the second trench T2 and mayinclude at least one of silicon nitride (SiN), silicon oxynitride(SiON), silicon oxide (SiO2), silicon oxycarbonitride (SiOCN), or acombination thereof.

The first high-k film 31 may be conformally formed along the sidewalland the bottom surface of the first trench T1. The first high-k film 31may entirely cover the sidewall of the first trench T1. Thus, the heightof the uppermost portion of the upper surface of the first high-k film31 may be same as that of the upper surface of the first spacer 21.However, exemplary embodiments are not limited to the example givenabove.

The second high-k film 32 may be conformally formed along the sidewalland the bottom surface of the second trench T2. The second high-k film32 may entirely cover the sidewall of the second trench T2. Thus, theheight of the uppermost portion of the upper surface of the secondhigh-k film 32 may be same as that of the upper surface of the secondspacer 22. However, exemplary embodiments are not limited to the examplegiven above.

The first high-k film 31 and the second high-k film 32 may include ahigh-k material having a higher dielectric constant than a silicon oxidefilm. For example, the high-k films 31 and 32 may include materialsselected from the group consisting of HfSiON, HfO₂, ZrO₂, Ta₂O₅, TiO₂,SrTiO₃ or (Ba,Sr)TiO₃, and so on. Such high-k films 31 and 32 may beformed to a proper thickness depending on a type of the device intendedto be formed.

Although not illustrated in FIG. 11, in some exemplary embodiments, aninterface film may be included between the high-k films 31 and 32 andthe substrate 10. The interface film may be formed along the bottomsurfaces of the trenches T1 and T2. The interface film 30 may play arole of preventing a defective interface between the substrate 10 andthe high-k films 31 and 32. The interface film may include a lowdielectric material layer having a dielectric constant (k) of 9 orlower, such as a silicon oxide film (k is approximately 4) or a siliconoxynitride film (k is approximately 4 to 8 depending on content ofoxygen atoms and nitrogen atoms). Alternatively, the interface film maybe formed of silicate, or a combination of films exemplified above.

The first gate pattern 61 may include a first function film 41 and afirst filling film 51. The first function film 41 may be conformallyformed along the bottom surface and the side surface of the first trenchT1, and the first filling film 51 may fill the portion not filled withthe first function film 41.

The second gate pattern 62 may include a second function film 42 and asecond filling film 52. The second function film 42 may be conformallyformed along the bottom surface and the side surface of the secondtrench T2, and the second filling film 52 may fill the portion notfilled with the second function film 42.

The function films 41 and 42 may include TiSiN. In this case, the Siconcentration in the first function film 41 may be lower than the Siconcentration Si in the second function film 42. As a result, thethreshold voltage of the transistor in the first region I may be lowerthan that of the transistor in the second region II.

The first source/drain 91 may be formed on the side surface of the firstgate pattern 61. The second source/drain 92 may be formed on the sidesurface of the second gate pattern 62. A portion between the firstsource/drain 91 of the first fin F1 may be defined as a first channelregion C1. Further, a portion between the second source/drain 92 of thesecond fin F2 may be defined as a second channel region C2.

The semiconductor device shown in FIGS. 10 and 11 may correspond to thatshown in FIG. 1. The first channel region C1 and the second channelregion C2 of FIGS. 10 and 11 may correspond to the first channel region1110 and the second channel region 1210 of FIG. 1. Further, the high-kfilms 31 and 32 and the interface film in FIGS. 10 and 11 maycorrespond, respectively, to the first gate insulating film 1120 and thesecond gate insulating film 1220 in FIG. 1. Further, the function films41 and 42 in FIGS. 10 and 11 may correspond, respectively, to the firstfunction film 1130 and the second function film 1230 in FIG. 1. Finally,the filling films 51 and 52 in FIGS. 10 and 11 may correspond,respectively, to the first filling film 1140 and the second filling film1240 in FIG. 1.

Thus, the gate stack structure of FIG. 1 may be implemented as thefin-type structure of FIGS. 10 and 11.

Hereinbelow, a semiconductor device according to some exemplaryembodiments will be described with reference to FIGS. 2 and 12. In thefollowing description, the description previously given for theexemplary embodiments already provided above will not be described hereor will be described as briefly as necessary for the sake of brevity.

FIG. 12 is a cross sectional view provided to explain a semiconductordevice according to some exemplary embodiments.

As shown in FIGS. 2 and 12, the first function film 1130 and the secondfunction film 1230 of FIG. 2 may be formed in the fin-type structure,which is the semiconductor device in FIG. 12.

The first function film 41 may have a structure in which the firstinterfacial function film 41 a and the first barrier function film 41 bare alternately stacked. Although each of the first interfacial functionfilms 41 a and the first barrier function films 41 b are shown as a pairin the drawings, in some embodiments, each of the first interfacialfunction films 41 a and the first barrier function films 41 b may bemore than two, or may be one.

The second function film 42 may have a structure in which the secondinterfacial function films 42 a and the second barrier function films 42b are alternately stacked. Although each of the second interfacialfunction films 42 a and the second barrier function films 42 b are shownas a pair in the drawings, in some embodiments, each of the secondinterfacial function films 42 a and the second barrier function films 42b may be more than two, or may be one.

Hereinbelow, a semiconductor device according to some exemplaryembodiments will be described with reference to FIGS. 1, 13 and 14. Inthe following description, the previous description of exemplaryembodiments already provided above will not be described here or will bedescribed as briefly as necessary for the sake of brevity.

FIG. 13 is a layout view provided to explain a semiconductor deviceaccording to some exemplary embodiments, and FIG. 14 is a crosssectional view taken on lines E1-E1 and E2-E2 of FIG. 13.

As shown in FIGS. 1, 13 and 14, a semiconductor device according to someembodiments of the present disclosure includes a substrate 500, verticalchannel regions 310 and 410, upper sources/drains 312 and 412, lowersource/drains 311 and 411, interlayer insulating films 300 and 400, gateinsulating films 320 and 420, function films 330 and 430, and fillingfilms 340 and 440.

The substrate 500 includes a first region I and second regions II.

The interlayer insulating films 300 and 400 may be formed on thesubstrate 500. The interlayer insulating films 300 and 400 may include afirst interlayer insulating film 300 formed in the first region I and asecond interlayer insulating film 400 formed in the second region II.

The vertical channel regions 310 and 410 may be formed through theinterlayer insulating films 300 and 400. The upper source/drain regions312 and 412 are formed on the upper portions of the vertical channelregions 310 and 410, and the lower source/drain regions 311 and 411 areformed on the lower portions of the vertical channel regions 310 and410.

The gate insulating films 320 and 420, the function films 330 and 430,and the filling films 340 and 440 may be formed on the lateral sides ofthe vertical channel regions 310 and 410 in a horizontal direction. Thegate insulating films 320 and 420 may horizontally surround the verticalchannel regions 310 and 410, and may be conformally formed along theupper and lower surfaces of the interlayer insulating films 300 and 400.The function films 330 and 430 are conformally formed on the gateinsulating films 320 and 420, and the filling films 340 and 440 may fillthe portions left unfilled by the function films 330 and 430.

In each regions, the thicknesses of the gate insulating films 320 and420, the function films 330 and 430, and the filling films 340 and 440may be equally the first thickness H1, the second thickness H2, and thethird thickness H3, respectively.

The function films 330 and 430 may include a first function film 330 inthe first region I and a second function film 430 in the second regionII. The first function film 330 and the second function film 340 mayinclude TiSiN. The Si concentration in the first function film 330 maybe less than the Si concentration in the second function film 340.

Accordingly, the threshold voltage in the vertical columnar FET (V-FET)structure may be lower in the first region I than in the second regionII.

The semiconductor device shown in FIGS. 13 and 14 may correspond to thatshown in FIG. 1. Specifically, the first region I and the second regionII in FIGS. 13 and 14 may correspond to the first region I and thesecond region II in FIG. 1, respectively. In addition, the verticalchannel regions 310 and 410 in FIGS. 13 and 14 may correspond to thefirst channel region 1110 and the second channel region 1210,respectively.

Further, the gate insulating films 320 and 420 in FIGS. 13 and 14 maycorrespond, respectively, to the first gate insulating film 1120 and thesecond gate insulating film 1220 in FIG. 1. Further, the function films330 and 430 in FIGS. 13 and 14 may correspond, respectively, to thefirst function film 1130 and the second function film 1230 in FIG. 1.Further, the filling films 340 and 440 in FIGS. 13 and 14 maycorrespond, respectively, to the first filling film 1140 and the secondfilling film 1240 in FIG. 1.

The gate stack structure of FIG. 1 may be implemented as the V-FETstructure of FIGS. 13 and 14. In the drawings, the number of thevertical channel regions is shown as one, but this is provided only forillustrative purpose and exemplary embodiments are not limited thereto.In some embodiments of the present disclosure, there may be two or morevertical channel regions that are vertically spaced from one another andstacked.

Hereinbelow, a semiconductor device according to some exemplaryembodiments will be described with reference to FIGS. 2 and 15 In thefollowing description, previous description of exemplary embodimentsalready provided above will not be described here or will be describedas briefly as necessary for the sake of brevity.

FIG. 15 are cross sectional views provided to explain a semiconductordevice according to some exemplary embodiments.

As shown in FIGS. 2 and 15, the first function film 1130 and the secondfunction film 1230 in FIG. 2 may be formed in the V-FET structure, whichis the semiconductor device in FIG. 15.

The first function film 330 may have a structure in which the firstinterfacial function filmfilms 330 a and the first barrier functionfilms 330 b are alternately stacked. Although the first interfacialfunction films 330 a and the first barrier function films 330 b are eachshown as a pair in the drawings, in some embodiments, the firstinterfacial function films 330 a and the first barrier function films330 b may each be more than two, or may be one.

The second function film 430 may have a structure in which the secondinterfacial function film 430 a and the second barrier function film 430b are alternately stacked. Although the second interfacial function film430 a and the second barrier function film 430 b are each shown as apair in the drawings, in some embodiments, the second interfacialfunction film 430 a and the second barrier function film 430 b may eachbe more than two, or may be one.

Hereinbelow, a method of fabricating a semiconductor device according tosome exemplary embodiments will be explained with reference to FIGS. 1and 16 to 18. In the following description, previous description of theexemplary embodiments already provided above will not be described hereor will be described as briefly as necessary for the sake of brevity.

FIGS. 16 to 18 are views illustrating intermediate stages offabrication, provided to explain the method for fabricating thesemiconductor device according to some exemplary embodiments.

As shown in FIG. 16, a first gate insulating film 1120 is formed on afirst channel region 1110 in a first region I, and a first Ti film 1130a and a first N film 1130 b are sequentially formed on a first gateinsulating film 1120. At this time, the order of the first Ti film 1130a and the first N film 1130 b may be reversed.

Likewise, in the second region II, a second gate insulating film 1220 isformed on a second channel region 1210, and a second Ti film 1230 a anda second N film 1230 b are sequentially formed on a second gateinsulating film 1220. At this time, the order of the second Ti film 1230a and the second N film 1230 b may be reversed.

At this time, the first gate insulating film 1120 and the second gateinsulating film 1220 may be formed with the first thickness H1. Each ofthe first Ti film 1130 a plus the first N film 1130 b, and the second Tifilm 1230 a plus the second N film 1230 b, may be formed with the secondthickness H2.

Next, a first heat treatment 1300 is performed in the first region I andthe second region II.

Then, as shown in FIG. 17, the first heat treatment 1300 may cause thefirst Ti film 1130 a and the first N film 1130 b to become the firstfunction film 1130, and the second Ti film 1230 a and the second N film1230 b to become the second function film 1230.

Then, the first doping 1400 a may be performed in the first region I,and the second doping 1400 b may be performed in the second region II.

Both the first doping 1400 a and the second doping 1400 b may be Sidoping. At this time, the amount of Si doping of the second doping 1400b may be greater than that of the first doping 1400 a. This may beperformed by varying the doping density, or by varying the doping time.

Then, as shown in FIG. 18, the Si concentration of the first functionfilm 1130 and that of the second function film 1230 are different fromeach other.

Next, as shown in FIG. 1, a first filling film 1140 and a second fillingfilm 1240 are formed on the first function film 1130 and the secondfunction film 1230, respectively.

A method for fabricating a semiconductor device according to someembodiments of the present disclosure may implement a transistor havinga multi-threshold voltage through the concentration of a function filmwithout forming a barrier film and a work function adjusting film.

In particular, the process of forming the function films of the samethickness in different regions can be much simpler and lower in costthan the method of controlling the thickness of the work functionadjusting film differently. As a result, the semiconductor manufacturingcost and efficiency can be significantly lowered.

Hereinbelow, a method for fabricating a semiconductor device accordingto some exemplary embodiments will be explained with reference to FIGS.2 and 19 to 22. In the following description, previous description ofexemplary embodiments already provided above will not be described hereor will be described as briefily as necessary for the sake of brevity.

FIGS. 19 to 22 are views illustrating intermediate stages offabrication, provided to explain a method for fabricating asemiconductor device according to some exemplary embodiments.

As shown in FIG. 19, a first gate insulating film 1120 is formed on afirst channel region 1110 in a first region I, and a first interfacialfunction film 1131 a is formed on the first gate insulating film 1120with a thickness a1.

A second gate insulating film 1220 is formed on a second channel region1210 in a second region II, and a second interfacial function film 1231a is formed on the second gate insulating film 1220 with a thickness c1.

The thickness a1 and the thickness c1 may be different from each other.The thickness c1 may be greater than the thickness a1. However, as willbe described below, as long as the thickness a1+a2 is lower than thethickness c1+c2, whether the thickness c1 is greater or less than thethickness a1 is not limiting on the exemplary embodiments.

The first interfacial function film 1131 a and the second interfacialfunction film 1231 a may be formed by an atomic layer deposition (ALD)method.

Next, as shown in FIG. 20, in the first region I, the first barrierfunction film a is formed on the first interfacial function film 1131 awith a thickness b1.

In the second region II, the second barrier function film 1233 a isformed on the second interfacial function film 1231 a with a thicknessd1.

The thickness b1 and the thickness d1 may be different from each other.The thickness b1 may be greater than the thickness d1. However, as willbe described below, as long as the thickness b1+b2 is lower than thethickness d1+d2, whether the thickness b1 is greater or less than thethickness d1 is not limiting on the exemplary embodiments.

The first barrier function film 1133 a and the second barrier functionfilm 1233 a may be formed in a soak method.

Next, as shown in FIG. 21, in the first region I, the first interfacialfunction film 1131 b is formed on the first barrier function film 1131 bwith a thickness a2.

In the second region II, the second interfacial function film 1231 b isformed on the second barrier function film 1233 a with a thickness c2.

At this time, the thickness a1+a2 may be less than the thickness c1+c2.

The first interfacial function film 1131 b and the second interfacialfunction film 1231 b may be formed by an atomic layer deposition (ALD)method.

Next, as shown in FIG. 22, in the first region I, the first barrierfunction film 1133 b is formed on the first interfacial function film1131 b with a thickness b2.

In the second region II, the second barrier function film 1233 b isformed on the second interfacial function film 1231 b with a thicknessd2.

At this time, the thickness b1+b2 may be greater than the thicknessd1+d2.

However, the thickness a1+a2+b1+b2 may be the second thickness H2 whichis the same as the thickness c1+c2+d1+d2.

The first barrier function film 1133 b and the second barrier functionfilm 1233 b may be formed in a soak method.

The stacked structure of the first interfacial function films 1131 a and1131 b and the first barrier function films 1133 a and 1133 b may becompleted with the first function film 1130, and the second interfacialfunction films 1231 a and 1231 b and the second barrier function films1233 a and 1233 b may be completed with the second function film 1230.

At this time, the processes of forming the first function film 1130 andthe second function film 1230 may all be performed in-situ. However,exemplary embodiments are not limited to the example given above. Thus,the semiconductor device manufacturing method according to someembodiments of the present disclosure can provide a semiconductor devicewith few defects and high efficiency.

Next, As shown in FIG. 2, the first filling film 1140 may be formed onthe first function film 1130, and the second filling film 1240 may beformed on the second function film 1230.

While the present inventive concept has been particularly shown anddescribed with reference to exemplary embodiments thereof, it will beunderstood by those of ordinary skill in the art that various changes inform and details may be made therein without departing from the spiritand scope of the present inventive concept as defined by the followingclaims. It is therefore desired that the present embodiments beconsidered in all respects as illustrative and not restrictive,reference being made to the appended claims rather than the foregoingdescription to indicate the scope of the invention.

What is claimed is:
 1. A semiconductor device comprising: first and second gate stack structures formed in first and second regions, respectively, wherein the first gate stack structure is formed adjacent to a first channel region and the second gate stack structure is formed adjacent to a second channel region, wherein the first gate stack structure comprises: a first gate insulating film having a first thickness formed on the first channel region; a first function film having a second thickness formed on the first gate insulating film; and a first filling film having a third thickness formed on the first function film; wherein the second gate stack structure comprises: a second gate insulating film having the first thickness formed on the second channel region; a second function film having the second thickness formed on the second gate insulating film; and a second filling film having the third thickness formed on the second function film, wherein the first and second function films comprise TiN, and wherein Si concentrations of the first and second function films are different from each other.
 2. The semiconductor device of claim 1, wherein the first and second function films are a single film.
 3. The semiconductor device of claim 1, wherein the first function film comprises a first interfacial function film and a first barrier function film alternately stacked, and wherein the second function film comprises a second interfacial function film and a second barrier function film alternately stacked.
 4. The semiconductor device of claim 3, wherein the first and second interfacial function films comprise TIN, and wherein the first and second barrier function films comprise Si.
 5. The semiconductor device of claim 3, wherein a ratio of the thickness of the first barrier function film relative to the thickness of the first interfacial function film, and wherein a ratio of the thickness of the second barrier function film relative to the thickness of the second interfacial function film are different from each other.
 6. The semiconductor device of claim 3, wherein the first and second interfacial function films comprise amorphous TIN, and wherein the first and second barrier function films comprise crystalline Si
 7. The semiconductor device of claim 1, wherein the first and second channel regions comprise Si.
 8. The semiconductor device of claim 1, wherein the first gate insulating film comprises a first interfacial layer and a first high-k film on the first interfacial layer, wherein the second gate insulating film comprises a second interfacial layer and a second high-k film on the second interfacial layer, and wherein the first and second high-k films have a higher dielectric constant than a silicon oxide film.
 9. The semiconductor device of claim 1, wherein the first function film comprises TiSiN, and wherein the second function film comprises TiN but not Si.
 10. A semiconductor device, comprising: a substrate comprising first and second regions; first and second channel regions formed in the first and second regions, respectively; first and second gate insulating films formed on the first and the second channel regions, respectively; first and second function films formed on the first and second gate insulating films, respectively, and wherein a Si concentration of the first function film and a Si concentration of the second function film are different from each other; and first and second filling films formed on the first and the second function films, respectively, wherein the first and second function films are a TiSiN single film, or multiple films including a TiN film and a Si film alternately stacked.
 11. The semiconductor device of claim 10, wherein the first and second channel regions are first and second nanowires spaced apart from the substrate, respectively, wherein the first gate insulating film, the first function film, and the first filling film surround the first nanowire, and wherein the second gate insulating film, the second function film, and the second filling film surround the second nanowire.
 12. The semiconductor device of claim 11, further comprising: a first source/drain connecting with the first channel region on opposite sides of the first channel region, and a second source/drain connecting with the second channel region on opposite sides of the second channel region.
 13. The semiconductor device of claim 12, wherein the first and the second channel regions extend in a horizontal direction, wherein the first source/drain is in contact with an upper surface and a bottom surface of the first channel region, respectively, and wherein the second source/drain is in contact with an upper surface and a bottom surface of the second channel region, respectively.
 14. The semiconductor device of claim 10, wherein the substrate comprises: a first fin protruding in the first region and extending in a first direction; and a second fin protruding in the second region and extending in a second direction, and wherein the first and second channel regions are on upper portions of the first and second fins, respectively.
 15. The semiconductor device of claim 14, further comprising: a first recess formed on either side of the first channel region, within the first fin; a first source/drain formed in the first recess; a second recess formed on either side of the second channel region, within the second fin; and a second source/drain formed in the second recess.
 16. A method manufacturing a semiconductor device, comprising: forming a first gate insulating film on a first channel region in a first region; forming above the first gate insulating film a first Ti film and a first N film; forming a second gate insulating film on a second channel in a second region adjacent to the first region; forming above the second gate insulating film a second Ti film and a second N film, wherein each of the first and second gate insulating films have a first thickness H1, a a first combination of the first Ti film and the first N film have a second thickness H2, and a second combination of the second Ti film and the second N film have the second thickness H2, performing a heat treatment in first and second regions to cause the first Ti film and the first N film to become a first function film and the second Ti film and the second N film to become a second function film; performing a first doping in the first region and a second doping in the second region, wherein both the first doping and the second doping are Si doping; and forming a first filling film and a second filling film, respectively, on said first and second function films.
 17. The method of claim 16, wherein the first and second N films directly contact, respectively, the first and second gate insulating films.
 18. The method of claim 16, wherein the first and second Ti films directly contact, respectively, the first and second gate insulating films.
 19. The method of claim 16, wherein the amount of Si doping in the second doping is greater than the amount of Si doping in first doping.
 20. The method of claim 16, wherein concentrations of Si in the first and second function films are different from each other. 